The present invention relates to a dynamic semiconductor memory device with decreased clocks, and more particularly, to an improvement of a semiconductor memory device having dynamic memory cells each of which comprises one transistor and one capacitor.
In general, a dynamic semiconductor memory device comprises a number of memory cells arranged in an array or matrix comprising of intersecting word lines and bit lines. Each of the bit lines is associated with a sense amplifier. Each of the memory cells connected to one sense amplifier comprises one transistor and one capacitance. During a precharge period, a bit line is charged to V.sub.CC (power supply voltage). In a reading operation, the sense amplifier amplifies the stored charge signal so as to be read out. After the reading operation, a dynamic restore operation is effected by charging the capacitance with charges on the bit line.
A cross reference in this field is: IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-15, No. 5, October 1980, pp 831-839,"A High Performance Sense Amplifier for a 5 V Dynamic RAM".
In an example of the prior-art devices, there is known a dynamic semiconductor memory device in which a pull up circuit for charging up each bit line after the reading operation is not included. The problem in this conventional device is that, after the reading operation, charges on each bit line have leaked out through the associated sense amplifier or due to a junction leak that lowers the potential of the bit line so that the dynamic restore operation is not sufficiently effected, as hereinafter described in detail. Since charges are not sufficiently restored in the cell capacitance, there are the disadvantages of low tolerance against soft errors which have been taken into consideration in recent years, or of the common occurrence of restore errors.
In another example of a known dynamic semiconductor memory device, a pull up circuit is associated with each bit line so that each bit line is charged up after the reading operation. In this second conventional example, the above mentioned problem of an insufficient restore operation is eliminated. However, since a number of clock signals must be applied to many points of the dynamic semiconductor memory device of this second conventional example, difficulties occur in setting the potential levels of these clock signals, or in determining the timings of these clock signals to be applied.